mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 142

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock, Reset and Power Management (S12CPMU_UHV)
142
WRTMASK
RSBCK
CR[2:0]
WCOP
Field
2–0
7
6
5
Window COP Mode Bit — When set, a write to the CPMUARMCOP register must occur in the last 25% of the
selected period.A write during the first 75% of the selected period generates a COP reset.As long as all writes
occur during this window, $55 can be written as often as desired.Once $AA is written after the $55, the time-out
logic restarts and the user must wait until the next window before writing to CPMUARMCOP.
the duration of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in Active BDM mode.
1 Stops the COP and RTI counters whenever the part is in Active BDM mode.
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits
while writing the CPMUCOP register. It is intended for BDM writing the RSBCK without changing the content of
WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an effect with this write of CPMUCOP
1 Write of WCOP and CR[2:0] has no effect with this write of CPMUCOP.
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see
Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period.A COP counter
time-out causes a System Reset.This can be avoided by periodically (before time-out) initializing the COP
counter via the CPMUARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at
highest time-out period (
(Does not count for “write once”.)
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in Special Mode
CR2
Table 4-13. COP Watchdog Rates if COPOSCSEL1=0.
0
0
0
0
1
1
1
1
Table 4-12. CPMUCOP Field Descriptions
MC9S12VR Family Reference Manual,
2
Preliminary - Subject to Change Without Notice
24
CR1
cycles) in normal COP mode (Window COP mode disabled):
0
0
1
1
0
0
1
1
(default out of reset)
CR0
0
1
0
1
0
1
0
1
Description
(COPCLK is either IRCCLK or
OSCCLK depending on the
Cycles to time-out
COPOSCSEL0 bit)
COP disabled
COPCLK
2
2
2
2
2
2
2
Rev. 2.2
14
16
18
20
22
23
24
Table 4-13
Freescale Semiconductor
Table 4-13
and
Table
shows
4-14).