mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 63

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

1
2.3.12
Freescale Semiconductor
Address 0x0242
Read: Anytime
Write: Anytime
DDRT
DDRT
DDRT
Field
Reset
1-0
3
2
W
R
Data Direction Register port T —
This bit determines whether the pin is an input or output
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. The enabled
routed LINPHY forces the I/O state to be an input (LPTXD). Else the TIM forces the I/O state to be an output for a
TIM port associated with an enabled TIM output compare. In these cases the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Data Direction Register port T —
This bit determines whether the pin is an input or output.
Depending on the configuration of the enabled SPI the I/O state will be forced to be input or output. The enabled
routed LINPHY forces the I/O state to be an output (LPRXD). Else the TIM forces the I/O state to be an output for a
TIM port associated with an enabled TIM output compare. In these cases the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Data Direction Register port T —
This bit determines whether the pin is an input or output.
Depending on the configuration of the enabled routed SCI0 the I/O state will be forced to be input or output. The
enabled routed LINPHY forces the I/O state to be an output (LPDR[LPDR1]). Else the TIM forces the I/O state to be
an output for a TIM port associated with an enabled TIM output compare. In these cases the data direction bit will
not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port T Data Direction Register (DDRT)
0
0
7
0
0
6
Figure 2-10. Port T Data Direction Register (DDRT)
Table 2-12. DDRT Register Field Descriptions
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
5
0
0
0
0
4
Description
DDRT3
0
3
DDRT2
Port Integration Module (S12VRPIMV2)
0
2
DDRT1
Access: User read/write
0
1
DDRT0
0
0
63
1