mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 315

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

10.3.2.3
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Freescale Semiconductor
Module Base + 0x0000
RXEDGIF
BERRIF
BERRV
Reset
BKDIF
Field
7
2
1
0
W
R
RXEDGIF
Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,
rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.
0 No active edge on the receive input has occurred
1 An active edge on the receive input has occurred
Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and
a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.
0 A low input was sampled, when a high was expected
1 A high input reassembled, when a low was expected
Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value
sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an
interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.
0 No mismatch detected
1 A mismatch has occurred
Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is
received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing
a “1” to it.
0 No break signal was received
1 A break signal was received
SCI Alternative Status Register 1 (SCIASR1)
0
7
= Unimplemented or Reserved
Figure 10-6. SCI Alternative Status Register 1 (SCIASR1)
0
0
6
MC9S12VR Family Reference Manual, Rev. 2.2
Table 10-6. SCIASR1 Field Descriptions
Preliminary - Subject to Change Without Notice
0
0
5
0
0
4
Description
0
0
3
Serial Communication Interface (S12SCIV5)
BERRV
0
2
BERRIF
0
1
BKDIF
0
0
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