mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 460

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
64 KByte Flash Module (S12FTMRG64K512V1)
17.2
The Flash module contains no signals that connect off-chip.
17.3
This section describes the memory map and registers for the Flash module. Read data from unimplemented
memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space
in the Flash module will be ignored by the Flash module.
.
17.3.1
The S12 architecture places the P-Flash memory between global addresses
shown in Table
460
1
Global Address (in Bytes)
See NVMRES description in
0x0_0400 – 0x0_05FF
0x0_4000 – 0x0_7FFF
0x0_0000 - 0x0_03FF
External Signal Description
Memory Map and Registers
Module Memory Map
Writing to the Flash registers while a Flash command is executing (that is
indicated when the value of flag CCIF reads as ’0’) is not allowed. If such
action is attempted the write operation will not change the register value.
Writing to the Flash registers is allowed when the Flash is not busy
executing commands (CCIF = 1) and during initialization right after reset,
despite the value of flag CCIF in that case (refer to
complete description of the reset sequence).
17-2.The P-Flash memory map is shown in
Section 17.4.3
(Bytes)
16,284
1,024
Size
512
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Table 17-1. FTMRG Memory Map
Register Space
EEPROM Memory
NVMRES
1
CAUTION
=1 : NVM Resource area (see
Figure
Description
Section 17.6
Rev. 2.2
17-2.
Figure
0x3_0000 and 0x3_FFFF as
17-2)
for a
Freescale Semiconductor

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