mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 189

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Figure 5-9
there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit
time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target
wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives
it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting
the bit time.
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Start of Bit Time
Start of Bit Time
Speedup Pulse
Target System
Target System
(Target MCU)
(Target MCU)
BDM Clock
BDM Clock
BKGD Pin
BKGD Pin
BKGD Pin
BKGD Pin
Perceived
Drive and
Perceived
Speedup
Drive to
Drive to
Pulse
Host
Host
shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target,
Figure 5-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
High-Impedance
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
10 Cycles
10 Cycles
R-C Rise
10 Cycles
10 Cycles
High-Impedance
Host Samples
High-Impedance
Host Samples
BKGD Pin
BKGD Pin
Background Debug Module (S12SBDMV1)
Speedup Pulse
High-Impedance
Next Bit
Earliest
Start of
Next Bit
Earliest
Start of
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