mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 148

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock, Reset and Power Management (S12CPMU_UHV)
4.3.2.15
The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features.
Read: Anytime
Write: Anytime
148
0x02F2
APICLK
Reset
APIES
APIEA
APIFE
Field
APIE
APIF
7
4
3
2
1
0
W
R
APICLK
Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if
APIFE = 0. APICLK cannot be changed if APIFE is set by the same write operation.
0 Autonomous Clock (ACLK) used as source.
1 Bus Clock used as source.
Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin
API_EXTCLK as shown in
0 If APIEA and APIFE are set, at the external pin API_EXTCLK periodic high pulses are visible at the end of
1 If APIEA and APIFE are set, at the external pin API_EXTCLK a clock is visible with 2 times the selected API
Autonomous Periodical Interrupt External Access Enable Bit — If set, the waveform selected by bit APIES
can be accessed externally. See device level specification for connectivity.
0 Waveform selected by APIES can not be accessed externally.
1 Waveform selected by APIES can be accessed externally, if APIFE is set.
Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer
when set.
0 Autonomous periodical interrupt is disabled.
1 Autonomous periodical interrupt is enabled and timer starts running.
Autonomous Periodical Interrupt Enable Bit
0 API interrupt request is disabled.
1 API interrupt will be requested whenever APIF is set.
Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API configured time has elapsed.
This flag can only be cleared by writing a 1.Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an
interrupt request.
0 API time-out has not yet occurred.
1 API time-out has occurred.
Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
0
Figure 4-19. Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
7
every selected period with the size of half of the minimum period (APIR=0x0000 in
Period.
= Unimplemented or Reserved
0
0
6
Table 4-17. CPMUAPICTL Field Descriptions
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Figure
0
0
5
4-20. See device level specification for connectivity of API_EXTCLK pin.
APIES
0
4
Description
APIEA
0
3
Rev. 2.2
APIFE
0
2
Table
Freescale Semiconductor
APIE
0
1
4-21).
APIF
0
0