mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 42

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Device Overview MC9S12VR-Family
1.10
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 5.4.1
Security and Section 17.5 Security.
1.11
Consult the S12 CPU manual and the S12SINT section for information on exception processing.
1.11.1
Table 1-9. lists all Reset sources and the vector locations. Resets are explained in detail in the
“Clock, Reset and Power Management
42
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Dynamic power mode: Wait
— This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will
Static power mode Pseudo-stop:
— In this mode the system clocks are stopped but the oscillator is still running and the real time
Static power mode: Stop
— The oscillator is stopped in this mode. By default, all clocks are switched off and all counters
Vector Address
Security
Resets and Interrupts
not execute instructions. The internal CPU clock is switched off. All peripherals can be active
in system wait mode. For further power consumption the peripherals can individually turn off
their local clocks. Asserting RESET, XIRQ, IRQ, or any other interrupt that is not masked ends
system wait mode.
interrupt (RTI) and watchdog (COP), Autonomous Periodic Interrupt (API) and ATD modules
may be enabled. Other peripherals are turned off. This mode consumes more current than
system STOP mode but, as the oscillator continues to run, the full speed wake up time from this
mode is significantly shorter.
and dividers remain frozen. The autonomous periodic interrupt (API), ATD, key wake-up and
the LIN physical layer transceiver modules may be enabled to wake the device.
Resets
$FFFC
$FFFE
$FFFE
$FFFE
$FFFE
Table 1-9. Reset Sources and Vector Locations
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
External pin RESET
Clock monitor reset
Reset Source
(S12CPMU_UHV)”.
Mask
None
None
None
None
None
CCR
Rev. 2.2
OSCE Bit in CPMUOSC register
Local Enable
None
None
None
None
Freescale Semiconductor
Chapter 4,