mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 129

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.3.2
This section describes all the S12CPMU_UHV registers and their individual bits.
Address order is as listed in
4.3.2.1
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency
range.
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct
PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in
PLL (no locking and/or insufficient stability).
Freescale Semiconductor
0x0034
Reset
W
If PLL has locked (LOCK=1)
R
Register Descriptions
S12CPMU_UHV Synthesizer Register (CPMUSYNR)
0
7
VCOFRQ[1:0]
Writing to this register clears the LOCK and UPOSC status bits.
f
frequency f
VCO
must be within the specified VCO frequency lock range. Bus
Figure 4-4. S12CPMU_UHV Synthesizer Register (CPMUSYNR)
Table
1
6
bus
Figure 4-3
4-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional
must not exceed the specified maximum.
Table 4-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
32MHz <= f
48MHz < f
0
5
Reserved
Reserved
f VCO
VCO
VCO
<= 50MHz
<= 48MHz
=
NOTE
NOTE
1
4
2 f REF
×
×
(
Clock, Reset and Power Management (S12CPMU_UHV)
SYNDIV
1
3
VCOFRQ[1:0]
SYNDIV[5:0]
00
01
10
11
+
1
)
0
2
0
1
0
0
129