mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 45

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
1.11.3.1
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module
“Introduction”.
1.11.3.2
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.11.3.3
Refer to the PIM section for reset configurations of all peripheral module ports.
1.11.3.4
The RAM arrays are not initialized out of reset.
1.12
The API_EXTCLK option which is described
(CPMUAPICTL)
1.13
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are
loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence. See
Table 1-11
Freescale Semiconductor
API external clock output (API_EXTCLK)
COP Configuration
and
Flash Configuration Reset Sequence Phase
Reset While Flash Command Active
I/O Pins
RAM
Table 1-12
is not available on S12VR-Family.
for coding
FOPT Register
NV[2:0] in
Table 1-11. Initial COP Rate Configuration
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
000
001
010
011
100
101
110
111
4.3.2.15 Autonomous Periodical Interrupt Control Register
COPCTL Register
CR[2:0] in
111
110
101
100
011
010
001
000
Device Overview MC9S12VR-Family
Section 17.1,
45