mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 136

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Clock, Reset and Power Management (S12CPMU_UHV)
136
RTIOSCSEL
OSCSEL0
Field
COP
1
0
RTI Clock Select— RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the
RTIOSCSEL bit re-starts the RTI time-out period.
RTIOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the RTIOSCSEL bit.
0 RTI clock source is IRCCLK.
1 RTI clock source is OSCCLK.
COP Clock Select 0 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP
(see also
If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit
does not re-start the COP time-out period.
When COPOSCSEL1=0,COPOSCSEL0 selects the clock source to the COP to be either IRCCLK or OSCCLK.
Changing the COPOSCSEL0 bit re-starts the COP time-out period.
COPOSCSEL0 can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the COPOSCSEL0 bit.
0 COP clock source is IRCCLK.
1 COP clock source is OSCCLK
Table 4-6. COPOSCSEL1, COPOSCSEL0 clock source select description
Table
COPOSCSEL1
4-6)
0
0
1
Table 4-5. CPMUCLKS Descriptions (continued)
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
COPOSCSEL0
0
1
x
Description
Rev. 2.2
COP clock source
OSCCLK
IRCCLK
ACLK
Freescale Semiconductor

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