mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 206

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

S12S Debug Module (S12SDBGV2)
6.3.2.3
Read: Anytime
Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.
206
Address: 0x0022
TSOURCE
TRCMOD
TALIGN
Reset
Field
3–2
6
0
W
R
Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU
system is secured, this bit cannot be set and tracing is inhibited.
This bit must be set to read the trace buffer.
0 Debug session without tracing requested
1 Debug session with tracing requested
Trace Mode Bits — See
change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries
into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored.
In Compressed Pure PC mode the program counter value for each instruction executed is stored. See
Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
0 Trigger at end of stored data
1 Trigger before storing data
Debug Trace Control Register (DBGTCR)
0
0
7
TRCMOD
00
01
10
11
TSOURCE
0
6
Figure 6-5. Debug Trace Control Register (DBGTCR)
Table 6-8. TRCMOD Trace Mode Bit Encoding
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Table 6-7. DBGTCR Field Descriptions
Section 6.4.5.2, “Trace Modes
0
0
5
0
0
4
Compressed Pure PC
Description
Description
Normal
Loop1
Detail
for detailed Trace Mode descriptions. In Normal Mode,
0
3
TRCMOD
Rev. 2.2
0
2
Freescale Semiconductor
0
0
1
TALIGN
Table
0
0
6-8.