mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 85

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

1
1
Address 0x026E
Address 0x026F
2.3.37
2.3.38
2.3.39
Freescale Semiconductor
Read: Anytime
Write: Anytime
Read: Anytime
Write: Anytime, write 1 to clear
Reset
Reset
Field
Field
PIEL
PIFL
W
W
3-0
3-0
R
R
Port L Interrupt Enable Register (PIEL)
Port L Interrupt Flag Register (PIFL)
Port AD Data Register (PT1AD)
0
0
0
0
7
7
Pin Interrupt Enable register port L —
This bit enables or disables the edge sensitive pin interrupt on the associated pin. For wakeup from stop mode
this bit must be set.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
Pin Interrupt Flag register port L —
This flag asserts after a valid active edge was detected on the related pin
can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the
associated interrupt enable bit is set.
1 Active edge on the associated bit has occurred
0 No active edge occurred
0
0
0
0
6
6
Figure 2-36. Port L Interrupt Enable Register (PIEL)
Figure 2-37. Port L Interrupt Flag Register (PIFL)
Table 2-39. PIEL Register Field Descriptions
Table 2-40. PIFL Register Field Descriptions
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
5
0
0
5
0
0
0
0
0
0
4
4
Description
Description
PIEL3
PIFL3
0
0
3
3
PIEL2
PIFL2
Port Integration Module (S12VRPIMV2)
0
0
2
2
(Section 2.4.4,
Access: User read/write
Access: User read/write
PIEL1
PIFL1
0
0
1
1
“Interrupts”). This
PIEL0
PIFL0
0
0
0
0
85
1
1