mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 267

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

8.3.2.7
This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and
the conversion counter.
Read: Anytime
Write: Anytime (No effect on (CC3, CC2, CC1, CC0))
Freescale Semiconductor
Module Base + 0x0006
ETORF
Reset
FIFOR
Field
SCF
7
5
4
W
R
SCF
Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN=1), the flag is set after each one is completed. This flag is cleared
when one of the following occurs:
0 Conversion sequence not completed
1 Conversion sequence has completed
External Trigger Overrun Flag — While in edge sensitive mode (ETRIGLE=0), if additional active edges are
detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the
following occurs:
0 No External trigger overrun error has occurred
1 External trigger overrun error has occurred
Result Register Overrun Flag — This bit indicates that a result register has been written to before its associated
conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because
the flag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been overwritten before it has been read
(i.e. the old data has been lost). This flag is cleared when one of the following occurs:
0 No overrun has occurred
1 Overrun condition exists (result register has been written while associated CCFx flag was still set)
ATD Status Register 0 (ATDSTAT0)
0
7
A) Write “1” to ETORF
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
A) Write “1” to FIFOR
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
A) Write “1” to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC=1 and a result register is read
= Unimplemented or Reserved
0
0
6
Figure 8-9. ATD Status Register 0 (ATDSTAT0)
MC9S12VR Family Reference Manual, Rev. 2.2
Table 8-16. ATDSTAT0 Field Descriptions
Preliminary - Subject to Change Without Notice
ETORF
0
5
FIFOR
0
4
Description
CC3
0
3
Analog-to-Digital Converter (ADC12B6CV2)
CC2
0
2
CC1
0
1
CC0
0
0
267