mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 137

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
4.3.2.7
This register controls the PLL functionality.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
Freescale Semiconductor
0x003A
FM1, FM0
Reset
Field
5, 4
W
R
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
is to reduce noise emission. The modulation frequency is f
S12CPMU_UHV PLL Control Register (CPMUPLL)
0
0
7
Write to this register clears the LOCK and UPOSC status bits.
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
Figure 4-10. S12CPMU_UHV PLL Control Register (CPMUPLL)
0
0
6
MC9S12VR Family Reference Manual, Rev. 2.2
Table 4-7. CPMUPLL Field Descriptions
Preliminary - Subject to Change Without Notice
Table 4-8. FM Amplitude selection
FM1
FM1
0
5
0
0
1
1
0
1
0
1
FM0
NOTE
NOTE
FM0
0
4
Description
FM Amplitude /
FM off
±1%
±2%
±4%
f
VCO
ref
Clock, Reset and Power Management (S12CPMU_UHV)
0
0
3
divided by 16. See
Variation
0
0
2
Table 4-8
0
0
1
for coding.
0
0
0
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