UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 106

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PSD module
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PSD module
The PSD module provides configurable Program and Data memories to the 8032 CPU core
(MCU). In addition, it has its own set of I/O ports and a PLD with 16 macrocells for general
logic implementation.
Ports A,B,C, and D are general purpose programmable I/O ports that have a port
architecture which is different from the I/O ports in the MCU module.
The PSD module communicates with the MCU module through the internal address, data
bus (A0-A15, D0-D7) and control signals (RD, WR, PSEN, ALE, RESET). The user defines
the Decoding PLD in the PSDsoft Development Tool and can map the resources in the PSD
module to any program or data address space.
PSD module.
Functional overview
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1 or 2 Mbit Flash memory. This is the main Flash memory. It is divided into eight equal-
sized blocks that can be accessed with user-specified addresses.
Secondary 256 Kbit Flash boot memory. It is divided into four equal-sized blocks thatat
can be accessed with user-specified addresses. This secondary memory brings the
ability to execute code and update the main Flash concurrently.
64 Kbit SRAM.
CPLD with 16 Output Micro Cells (OMCs} and 20 Input Micro Cells (IMCs). The CPLD
may be used to efficiently implement a variety of logic functions for internal and
external control. Examples include state machines, loadable shift registers, and
loadable counters.
Decode PLD (DPLD) that decodes address for selection of memory blocks in the PSD
module.
Configurable I/O ports (Port A,B,C and D) that can be used for the following functions:
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Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
Internal page register that can be used to expand the 8032 MCU module address
space by a factor of 256.
Internal programmable Power Management Unit (PMU) that supports a low-power
mode called Power-down mode. The PMU can automatically detect a lack of the 8032
CPU core activity and put the PSD module into Power-down mode.
Erase/WRITE cycles:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os
I/O ports may be configured as open-drain outputs
Flash memory - 100,000 minimum
PLD - 1,000 minimum
Data Retention: 15 year minimum (for Main Flash memory, Boot, PLD and
Configuration bits)
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Figure 49
shows the functional blocks in the