UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 57

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
10
Watchdog timer
The hardware watchdog timer (WDT) resets the UPSD323xx devices when it overflows. The
WDT is intended as a recovery method in situations where the CPU may be subjected to a
software upset. To prevent a system reset the timer must be reloaded in time by the
application software. If the processor suffers a hardware/software malfunction, the software
will fail to reload the timer. This failure will result in a reset upon overflow thus preventing the
processor running out of control.
In the Idle mode the watchdog timer and reset circuitry remain active. The WDT consists of
a 22-bit counter, the Watchdog Timer RESET (WDRST) SFR and Watchdog Key Register
(WDKEY).
Since the WDT is automatically enabled while the processor is running. the user only needs
to be concerned with servicing it.
The 22-bit counter overflows when it reaches 4194304 (3FFFFFH). The WDT increments
once every machine cycle.
This means the user must reset the WDT at least every 4194304 machine cycles (1.258
seconds at 40MHz). To reset the WDT the user must write a value between 00-7EH to the
WDRST register. The value that is written to the WDRST is loaded to the 7MSB of the 22-bit
counter. This allows the user to pre-loaded the counter to an initial value to generate a
flexible Watchdog time out period. Writing a “00” to WDRST clears the counter.
The watchdog timer is controlled by the watchdog key register, WDKEY. Only pattern
01010101 (=55H), disables the watchdog timer. The rest of pattern combinations will keep
the watchdog timer enabled. This security key will prevent the watchdog timer from being
terminated abnormally when the function of the watchdog timer is needed.
In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
processor while in Idle, the user should always set up a timer that will periodically exit Idle,
service the WDT, and re-enter Idle mode.
Watchdog reset pulse width depends on the clock frequency. The reset period is tf
x 2
The RESET pulse width is tf
Table 32.
Table 33.
WDKEY7
22
7 to 0
Bit
.
7
Watchdog timer key register (WDKEY: 0AEh)
WDKEY6
Description of the WDKEY Bits
WDKEY7
WDKEY0
Symbol
to
6
Enable or disable watchdog timer.
01010101 (=55h): disable watchdog timer. Others: enable watchdog timer
WDKEY5
5
OSC
x 12 x 2
WDKEY4
4
15
.
WDKEY3
3
Function
WDKEY2
2
WDKEY1
1
Watchdog timer
WDKEY0
OSC
0
57/189
x 12