UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 90

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

DDC interface
16.1.1
16.1.2
Table 60.
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Addr
SFR
D4
D5
D6
D7
DDCADR
RAMBUF
DDCDAT
DDCCO
Name
Reg
N
DDCDAT register
DDC1 DATA register for transmission (DDCDAT: 0D5h)
●
●
DDCADR register
Address pointer for DDC interface (DDCADR: 0D6h)
●
●
DDC SFR memory map
Table 61.
Bit
8-bit READ and WRITE register
Indicates DATA BYTE to be transmitted in DDC1 protocol
8-bit READ and WRITE register.
Address pointer with the capability of the post increment. After each access to
RAMBUF register (either by software or by hardware DDC1 interface), the content of
this register will be increased by one. It’s available both in DDC1, DDC2 (DDC2B,
DDC2B+, and DDC2AB) and system operation.
7
6
5
4
—
7
Description of the DDCON register bits
DDC_AX
EX_DAT
Symbol
SWENB
EX_DAT
—
6
SWEN
Reserved
0 = The SRAM has 128 bytes (Default)
1 = The SRAM has 256 bytes
Note: This bit is valid for DDC1 & DDC2b modes
0 = Data is automatically read from SRAM at the current location of
DDCADR and sent out via current DDC protocol. (Default)
1 = MCU is interrupted during the current data byte transmission period to
load the next byte of data to send out.
Note: This bit is valid for DDC1 & DDC2b modes
0 = Data is automatically read from SRAM at the current location of
DDCADR and sent out via current DDC protocol. (Default)
1 = MCU is interrupted during the current data byte transmission period to
load the next byte of data to send out.
This bit only affects DDC2b mode Operation:
0 = DDC2b I2C Address is A0/A1 (default)
1 = DDC2b I2C Address is AX. Least 3 significant address bits are ignored.
B
5
Bit Register Name
DDC_A
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
X
4
DDCIN
T
3
DDC1EN
2
Function
SWHIN
1
T
M0
0
Reset
Value
XX
00
00
00
xmit register
Addr pointer
Comments
DDC Ram
DDC Data
Register
register
Control
Buffer
DDC