UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 48

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupt system
5.11
Note:
Note:
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How interrupts are handled
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled
during following machine cycle. If one of the flags was in a set condition at S5P2 of the
preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL
to the appropriate service routine, provided this H/W generated LCALL is not blocked by any
of the following conditions:
●
●
●
The polling cycle is repeated with each machine cycle, and the values polled are the values
that were present at S5P2 of the previous machine cycle.
If an interrupt flag is active but being responded to for one of the above mentioned
conditions, if the flag is still inactive when the blocking condition is removed, the denied
interrupt will not be serviced. In other words, the fact that the interrupt flag was once active
but not serviced is not remembered. Every polling cycle is new.
The processor acknowledges an interrupt request by executing a hardware generated
LCALL to the appropriate service routine. The hardware generated LCALL pushes the
contents of the Program Counter on to the stack (but it does not save the PSW) and reloads
the PC with an address that depends on the source of the interrupt being vectored to as
shown in
Execution proceeds from that location until the RETI instruction is encountered. The RETI
instruction informs the processor that the interrupt routine is no longer in progress, then
pops the top two bytes from the stack and reloads the Program Counter. Execution of the
interrupted program continues from where it left off.
A simple RET instruction would also return execution to the interrupted program, but it would
have left the interrupt control system thinking an interrupt was still in progress, making future
interrupts impossible.
Table 24.
An interrupt of equal priority or higher priority level is already in progress.
The current machine cycle is not the final cycle in the execution of the instruction in
progress.
The instruction in progress is RETI or any access to the interrupt priority or interrupt
enable registers.
Table
Vector addresses
Timer 2+EXF2
2nd USART
1st USART
24.
Timer 0
Timer 1
Source
DDC
USB
Int0
Int1
I²C
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Vector address
004Bh
000Bh
0043h
003Bh
001Bh
0033h
0023h
002Bh
0003h
0013h