UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 125

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
22.11
Figure 54. Separate Space mode
Figure 55. Combined Space mode
Page register
The 8-bit Page Register increases the addressing capability of the MCU Core by a factor of
up to 256. The contents of the register can also be read by the MCU. The outputs of the
Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic.
Figure 56
internal data bus D0-D7. The MCU can write to or read from the Page Register. The Page
Register can be accessed at address location CSIOP + E0h.
RD
PSEN
VM REG BIT 3
VM REG BIT 4
VM REG BIT 1
VM REG BIT 2
VM REG BIT 0
shows the Page Register. The eight flip-flops in the register are connected to the
DPLD
RD
RS0
CSBOOT0-3
FS0-FS7
PSEN
DPLD
RS0
CSBOOT0-3
FS0-FS7
CS
Memory
Primary
Flash
OE
CS
Memory
Primary
Flash
OE
Secondary
CS
Memory
Flash
OE
RD
Secondary
CS
Memory
Flash
OE
CS
SRAM
OE
Memory blocks
CS
SRAM
OE
AI02869C
AI02870C
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