UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 150

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

RESET timing and device status at reset
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26.3
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RESET timing and device status at reset
Upon Power-up, the PSD module requires a Reset (RESET) pulse of duration t
V
the registers and sets the Flash memory into operating mode. After the rising edge of Reset
(RESET), the PSD module remains in the Reset mode for an additional period, t
the first memory access is allowed.
The Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, WRITE Strobe (WR, CNTL0) High, during Power-
on RESET for maximum security of the data contents and to remove the possibility of a byte
being written on the first edge of WRITE Strobe (WR). Any Flash memory WRITE cycle
initiation is prevented automatically when V
Warm RESET
Once the device is up and running, the PSD module can be reset with a pulse of a much
shorter duration, t
after a Warm RESET.
I/O pin, register and PLD status at RESET
Table 106
RESET, and Power-down mode. PLD outputs are always valid during Warm RESET, and
they are valid in Power-on RESET once the internal Configuration bits are loaded. This
loading is completed typically long before the V
PLD is active, the state of the outputs are determined by the PLD equations.
Reset of Flash Memory Erase and Program Cycles
A Reset (RESET) also resets the internal Flash memory state machine. During a Flash
memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the Flash
memory to the READ mode within a period of t
Figure 69. Reset (RESET) timing
CC
is steady. During this period, the device loads internal configurations, clears some of
V
RESET
CC
shows the I/O pin, register and PLD status during Power-on RESET, Warm
NLNH
Power-On Reset
Figure 69
. The same t
V
t NLNH-PO
CC
(min)
shows the timing of the Power-up and Warm RESET.
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
OPR
t OPR
period is needed before the device is operational
CC
is below V
NLNH-A
CC
ramps up to operating level. Once the
.
LKO
.
Warm Reset
t NLNH-A
t NLNH
t OPR
NLNH-PO
AI02866b
OPR
, before
after