UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 43

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
5
5.1
5.2
5.3
5.4
Interrupt system
There are interrupt requests from 10 sources as follows.
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External Int0 interrupt
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Timer 0 and 1 interrupts
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Timer 2 interrupt
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I
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2
C interrupt
INT0 external interrupt
2nd USART interrupt
Timer 0 interrupt
I
INT1 external interrupt (or ADC interrupt)
DDC interrupt
Timer 1 interrupt
USB interrupt
USART interrupt
Timer 2 interrupt
The INT0 can be either level-active or transition-active depending on Bit IT0 in register
TCON. The flag that actually generates this interrupt is Bit IE0 in TCON.
When an external interrupt is generated, the corresponding request flag is cleared by
the hardware when the service routine is vectored to only if the interrupt was transition
activated.
If the interrupt was level activated then the interrupt request flag remains set until the
requested interrupt is actually generated. Then it has to deactivate the request before
the interrupt service routine is completed, or else another interrupt will be generated.
Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1 which are set by an
overflow of their respective Timer/Counter registers (except for Timer 0 in Mode 3).
These flags are cleared by the internal hardware when the interrupt is serviced.
Timer 2 Interrupt is generated by TF2 which is set by an overflow of Timer 2. This flag
has to be cleared by the software - not by hardware.
It is also generated by the T2EX signal (Timer 2 External Interrupt P1.1) which is
controlled by EXEN2 and EXF2 Bits in the T2CON register.
The interrupt of the I
This flag is cleared by hardware.
2
C interrupt
2
C is generated by Bit INTR in the register S2STA.
Interrupt system
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