UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 128

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PLDs
23.2
128/189
See
Additionally, five bits are available in PMMR2 to block MCU control signals from entering the
PLDs. This reduces power consumption and can be used only when these MCU control
signals are not used in PLD logic equations.
Each of the two PLDs has unique characteristics suited for its applications. They are
described in the following sections.
Figure 57. PLD diagram
1. Port A is not available in the 52-pin package
Decode PLD (DPLD)
The DPLD, shown in
external components. The DPLD can be used to generate the following decode signals:
●
●
●
●
●
Section 25: Power management
8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms
each)
4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three
product terms each)
1 internal SRAM Select (RS0) signal (two product terms)
1 internal CSIOP Select signal (selects the PSD module registers)
2 internal Peripheral Select signals (Peripheral I/O mode).
DATA
BUS
73
73
DIRECT MACROCELL INPUT TO MCU DATA BUS
16
20
8
2
OUTPUT MACROCELL FEEDBACK
Figure
DECODE PLD
INPUT MACROCELL & INPUT PORTS
REGISTER
PAGE
CPLD
91, is used for decoding the address for PSD module and
PORT D INPUTS
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
ALLOC.
PT
for details on how to set the Turbo Bit.
8
4
1
1
2
20 INPUT MACROCELL
(PORT A,B,C)
MACROCELL
16 OUTPUT
PRIMARY FLASH MEMORY SELECTS
SECONDARY NON-VOLATILE MEMORY SELECTS
SRAM SELECT
CSIOP SELECT
PERIPHERAL SELECTS
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
MACROCELL
ALLOC.
EXTERNAL CHIP SELECTS
TO PORT A OR B 1
TO PORT B OR C
TO PORT D
MCELLAB
MCELLBC
AI06600
8
8
2