UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 24

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UPSD3234A-40U6T

Manufacturer Part Number
UPSD3234A-40U6T
Description
IC MCU 8032 64KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3234A-40U6T

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, UART/USART, USB
Peripherals
LVR, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
288KB (288K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPSD3234A-40U6T
Manufacturer:
STMicroelectronics
Quantity:
10 000
Architecture overview
2.11
Note:
24/189
Table 4.
Logical instructions
Table 5
Boolean operations (AND, OR, Exclusive OR, NOT) on bytes perform the operation on a bit-
by-bit basis. That is, if the Accumulator contains 00110101B and byte contains 01010011B,
then:
will leave the Accumulator holding 00010001B.
The addressing modes that can be used to access the <byte> operand are listed in
The ANL A, <byte> instruction may take any of the forms:
Boolean operations can be performed on any byte in the internal Data Memory space
without going through the Accumulator. The XRL <byte>, #data instruction, for example,
offers a quick and easy way to invert port bits, as in:
If the operation is in response to an interrupt, not using the Accumulator saves the time and
effort to push it onto the stack in the service routine.
The Rotate instructions (RL A, RLC A, etc.) shift the Accumulator 1 bit to the left or right. For
a left rotation, the MSB rolls into the LSB position. For a right rotation, the LSB rolls into the
MSB position.
The SWAP A instruction interchanges the high and low nibbles within the Accumulator. This
is a useful operation in BCD manipulations. For example, if the Accumulator contains a
ANL A, <byte>
ANL A,7FH(direct addressing)
ANL A, @R1 (indirect addressing)
ANL A,R6 (register addressing)
ANL A,#53H (immediate constant)
XRL P1, #0FFH.
DEC <byte>
INC <byte>
Mnemonic
INC DPTR
MUL AB
DIV AB
lists logical instructions for UPSD323xx devices. The instructions that perform
DA A
DEC
INC
Arithmetic instructions (continued)
<byte> = <byte> + 1
<byte> = <byte> – 1
DPTR = DPTR + 1
B = Mod[ A / B ]
Decimal Adjust
A = Int[ A / B ]
B:A = B x A
Operation
A = A + 1
A = A – 1
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Dir.
X
X
Accumulator and B only
Accumulator and B only
Addressing modes
Accumulator only
Accumulator only
Accumulator only
Data Pointer only
Ind.
X
X
Reg.
X
X
Table
Imm.
5.

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