UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 93

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Note:
1.
2.
3.
4.
5.
6.
7.
In case SWENB is set as high, interrupt service routine is finished within 133 machine cycle
in 40MHz System clock.
The maximum V
is interrupt period.
So the machine cycle be needed is calculated as below. For example,
●
●
●
If EX_DAT equals to LOW, it is meant the lower part is occupied by DDC1 operation and the
upper part is still free to the system. Nevertheless, the effect of the post increment just
applies to the part related to DDC1 operation. In other words, the system program is still
able to address the locations from 128 to 255 in the RAM buffer through MOVX command
but without the facility of the post increment. For example, the case of accessing 200 of the
RAM Buffer:
Figure 41. Transmission protocol in the DDC1 interface
Reset DDC1 enable (by default, DDC1 enable is cleared as LOW after Power-on
Reset).
Set SWENB as high (the default value is zero.)
Depending on the data size of EDID data, set EX_DAT as LOW (128 bytes) or HIGH
(256 bytes).
By using bulky moving commands (DDCADR, RAMBUF involved) to move the entire
EDID data to RAM buffer.
Reset SWENB to LOW.
Reset DDCADR to 00h.
Set DDC1 enable as HIGH.
When 40MHz system clock, 40µs = 133 x (25ns x 12); 133 machine cycle.
12MHz system clock, 40µs = 40 x (83.3ns x 12); 40 machine cycle.
8MHz system clock, 40µs = 26 x (125ns x 12); 26 machine cycle.
MOV R0, #200, and
MOVX A, @R0
SC
VCLK
DDC1INT
DDC1EN
SD
SYNC
t SU(DDC1)
1
(V
2
CLK
t H(VCLK)
3
) frequency is 25Khz (40µs). And the 9th clock of V
4
Hi-Z
5
6
t L(VCLK)
7
8
Max=40us
9
t DOV
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
HiZ
DDC interface
AI06652
1
B
SYNC
(V
93/189
CLK
)