UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 110

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UPSD3234A-40U6T

Manufacturer Part Number
UPSD3234A-40U6T
Description
IC MCU 8032 64KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3234A-40U6T

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, UART/USART, USB
Peripherals
LVR, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
288KB (288K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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PSD module register description and address offset
20
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PSD module register description and address offset
Table 84
base address. The CSIOP space is the 256 bytes of address that is allocated by the user to
the internal PSD module registers.
CSIOP space. The following section gives a more detailed description.
Table 84.
1. Other registers that are not part of the I/O ports.
Data In
Control
Data Out
Direction
Drive Select
Input Macrocell
Enable Out
Output Macrocells
AB
Output Macrocells
BC
Mask Macrocells
AB
Mask Macrocells
BC
Primary Flash
Protection
Secondary Flash
memory
Protection
PMMR0
PMMR2
Page
VM
Register Name
shows the offset addresses to the PSD module registers relative to the CSIOP
Register address offset
Port A Port B Port C Port D Other
0A
0C
00
02
04
08
20
22
06
0B
0D
01
03
05
07
09
20
21
22
23
1A
10
12
14
16
18
21
23
Table 84
1B
11
13
15
17
provides brief descriptions of the registers in
UPSD3234A, UPSD3234BV, UPSD3233B,
C0
C2
B0
B4
E0
E2
(1)
Reads Port pin as input, MCU I/O Input
mode
Selects mode between MCU I/O or
Address Out
Stores data for output to Port pins,
MCU I/O Output mode
Configures Port pin as input or output
Configures Port pins as either CMOS
or Open Drain on some pins, while
selecting high slew rate on other pins.
Reads Input Macrocells
Reads the status of the output enable
to the I/O Port driver
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
Blocks writing to the Output Macrocells
AB
Blocks writing to the Output Macrocells
BC
Read-only – Primary Flash Sector
Protection
Read-only – PSD module Security and
Secondary Flash memory Sector
Protection
Power Management Register 0
Power Management Register 2
Page Register
Places PSD module memory areas in
Program and/or Data space on an
individual basis.
Description

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