UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 31

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
The LJMP instruction encodes the destination address as a 16-bit constant. The instruction
is 3 bytes long, consisting of the opcode and two address bytes. The destination address
can be anywhere in the 64K Program Memory space.
The AJMP instruction encodes the destination address as an 11-bit constant. The
instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11 address
bits, followed by another byte containing the low 8 bits of the destination address. When the
instruction is executed, these 11 bits are simply substituted for the low 11 bits in the PC. The
high 5 bits stay the same. Hence the destination has to be within the same 2K block as the
instruction following the AJMP.
In all cases the programmer specifies the destination address to the assembler in the same
way: as a label or as a 16-bit constant. The assembler will put the destination address into
the correct format for the given instruction. If the format required by the instruction will not
support the distance to the specified destination address, a “Destination out of range”
message is written into the List file.
The JMP @A+DPTR instruction supports case jumps. The destination address is computed
at execution time as the sum of the 16-bit DPTR register and the Accumulator. Typically.
DPTR is set up with the address of a jump table. In a 5-way branch, for ex-ample, an integer
0 through 4 is loaded into the Accumulator. The code to be executed might be as follows:
The RL A instruction converts the index number (0 through 4) to an even number on the
range 0 through 8, because each entry in the jump table is 2 bytes long:
Table 13
ACALL, which differ in the format in which the subroutine address is given to the CPU. CALL
is a generic mnemonic which can be used if the programmer does not care which way the
address is encoded.
The LCALL instruction uses the 16-bit address format, and the subroutine can be anywhere
in the 64K Program Memory space. The ACALL instruction uses the 11-bit format, and the
subroutine must be in the same 2K block as the instruction following the ACALL.
In any case, the programmer specifies the subroutine address to the assembler in the same
way: as a label or as a 16-bit constant. The assembler will put the address into the correct
format for the given instructions.
Subroutines should end with a RET instruction, which returns execution to the instruction
following the CALL.
RETI is used to return from an interrupt service routine. The only difference between RET
and RETI is that RETI tells the interrupt control system that the interrupt in progress is done.
MOV DPTR,#JUMP TABLE
MOV A,INDEX_NUMBER
RL A
JMP @A+DPTR
JUMP TABLE:
AJMP CASE 0
AJMP CASE 1
AJMP CASE 2
AJMP CASE 3
AJMP CASE 4
shows a single “CALL addr” instruction, but there are two of them, LCALL and
Architecture overview
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