UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 29

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
2.13
Note:
Boolean instructions
The UPSD323xx devices contain a complete Boolean (single-bit) processor. One page of
the internal RAM contains 128 address-able bits, and the SFR space can support up to 128
addressable bits as well. All of the port lines are bit-addressable, and each one can be
treated as a separate single-bit port. The instructions that access these bits are not just
conditional branches, but a complete menu of move, set, clear, complement, OR and AND
instructions. These kinds of bit operations are not easily obtained in other architectures with
any amount of byte-oriented software.
The instruction set for the Boolean processor is shown in
direct addressing.
Bit addresses 00h through 7Fh are in the Lower 128, and bit addresses 80h through FFh
are in SFR space.
Note how easily an internal flag can be moved to a port pin:
In this example, FLAG is the name of any addressable bit in the Lower 128 or SFR space.
An I/O line (the LSB of Port 1, in this case) is set or cleared depending on whether the Flag
bit is '1' or '0.'
The Carry Bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit
instructions that refer to the Carry Bit as C assemble as Carry-specific instructions (CLR C,
etc.). The Carry Bit also has a direct address, since it resides in the PSW register, which is
bit-addressable.
The Boolean instruction set includes ANL and ORL operations, but not the XRL (Exclusive
OR) operation. An XRL operation is simple to implement in software. Suppose, for example,
it is required to form the Exclusive OR of two bits:
The software to do that could be as follows:
First, Bit 1 is moved to the Carry. If bit2 = 0, then C now contains the correct result. That is,
Bit 1 .XRL. bit2 = bit1 if bit2 = 0. On the other hand, if bit2 = 1, C now contains the
complement of the correct result. It need only be inverted (CPL C) to complete the
operation.
This code uses the JNB instruction, one of a series of bit-test instructions which execute a
jump if the addressed bit is set (JC, JB, JBC) or if the addressed bit is not set (JNC, JNB). In
the above case, Bit 2 is being tested, and if bit2 = 0, the CPL C instruction is jumped over.
JBC executes the jump if the addressed bit is set, and also clears the bit. Thus a flag can be
tested and cleared in one operation. All the PSW bits are directly addressable, so the Parity
Bit, or the general-purpose flags, for example, are also available to the bit-test instructions.
MOV C,FLAG
MOV P1.0,C
C = bit 1 .XRL. bit2
MOV C , bit1
JNB bit2, OVER
CPL C
OVER: (continue)
Table
12. All bits accesses are by
Architecture overview
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