UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 63

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Timer/counters (Timer 0, Timer 1 and Tim-
and set EXF2. Auto-reload mode is illustrated in the Standard Serial Interface (UART)
Figure
(TCLK, TCLK1)=1. It is described in conjunction with the serial port.
Table 40.
Table 41.
1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK
and TCLK.
TF2
Bit
7
7
6
5
4
3
2
1
0
25. The Baud Rate Generation mode is selected by (RCLK, RCLK1)=1 and/or
Timer/counter 2 control register (T2CON)
Description of the T2CON bits
Symbol
RCLK
TCLK
CP/RL2
EXEN2
EXF2
EXF2
C/T2
TR2
TF2
6
(1)
(1)
Timer 2 overflow flag. Set by a Timer 2 overflow, and must be cleared by
software. TF2 will not be set when either (RCLK, RCLK1)=1 or (TCLK,
TCLK)=1
Timer 2 external flag set when either a capture or reload is caused by a
negative transition on T2EX and EXEN2=1. When Timer 2 Interrupt is
enabled, EXF2=1 will cause the CPU to vector to the Timer 2 Interrupt
routine. EXF2 must be cleared by software
Receive clock flag (UART 1). When set, causes the serial port to use Timer
2 overflow pulses for its receive clock in Modes 1 and 3. TCLK=0 causes
Timer 1 overflow to be used for the receive clock
Transmit clock flag (UART 1). When set, causes the serial port to use Timer
2 overflow pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes
Timer 1 overflow to be used for the transmit clock
Timer 2 external enable flag. When set, allows a capture or reload to occur
as a result of a negative transition on T2EX if Timer 2 is not being used to
clock the serial port. EXEN2=0 causes Time 2 to ignore events at T2EX
Start/stop control for Timer 2. A logic 1 starts the timer
Timer or Counter select for Timer 2. Cleared for timer operation (input from
internal system clock, t
(negative edge triggered)
Capture/reload flag. When set, capture will occur on negative transition of
T2EX if EXEN2=1. When cleared, auto-reload will occur either with TImer 2
overflows, or negative transitions of T2EX when EXEN2=1. When either
(RCLK, RCLK1)=1 or (TCLK, TCLK)=1, this bit is ignored, and timer is
forced to auto-reload on Timer 2 overflow
RCLK
5
TCLK
4
CPU
); set for external event counter operation
EXEN2
3
Function
TR2
2
C/T2
1
CP/RL2
0
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