UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 118

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UPSD3234A-40U6T

Manufacturer Part Number
UPSD3234A-40U6T
Description
IC MCU 8032 64KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3234A-40U6T

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, UART/USART, USB
Peripherals
LVR, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
288KB (288K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Memory blocks
22.6.2
118/189
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to the Flash
memory with the byte that was intended to be written.
When using the Data Polling method during an Erase cycle,
the Data Polling Flag bit (DQ7) is '0' until the Erase cycle is complete. A '1' on the Error Flag
bit (DQ5) indicates a time-out condition on the Erase cycle; a '0' indicates no error. The
MCU can read any location within the sector being erased to get the Data Polling Flag bit
(DQ7) and the Error Flag bit (DQ5).
PSDsoft Express generates ANSI C code functions which implement these Data Polling
algorithms.
Figure 51. Data polling flowchart
Data toggle
Checking the Toggle Flag bit (DQ6) is a method of determining whether a Program or Erase
cycle is in progress or has completed.
When the MCU issues a Program instruction, the embedded algorithm begins. The MCU
then reads the location of the byte to be programmed in Flash memory to check status. The
Toggle Flag bit (DQ6) of this location toggles each time the MCU reads this location until the
embedded algorithm is complete. The MCU continues to read this location, checking the
Toggle Flag bit (DQ6) and monitoring the Error Flag bit (DQ5). When the Toggle Flag bit
(DQ6) stops toggling (two consecutive reads yield the same value), and the Error Flag bit
(DQ5) remains '0,' the embedded algorithm is complete. If the Error Flag bit (DQ5) is '1,' the
MCU should test the Toggle Flag bit (DQ6) again, since the Toggle Flag bit (DQ6) may have
changed simultaneously with the Error Flag bit (DQ5) (see
The Error Flag bit (DQ5) is set if either an internal time-out occurred while the embedded
algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit
that was not erased (not erased is logic '0').
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
at VALID ADDRESS
NO
READ DQ5 & DQ7
Figure 52
READ DQ7
START
DATA
DATA
FAIL
DQ7
DQ5
DQ7
= 1
=
=
YES
NO
NO
YES
YES
shows the Data Toggle algorithm.
PASS
AI01369B
Figure
Figure 51
52).
still applies. However,

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