UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 87

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
15.3
Table 54.
1. Interrupt Flag bit (INTR, SxSTA Bit 5) is cleared by Hardware as reading SxSTA register.
2. I
Table 55.
Address register (SxADR: S1ADR, S2ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will
respond when programmed as a slave receive/transmitter.
The Start/Stop Hold Time Detection and System Clock registers
included in the I
MCU frequency values supported. For example, with a system clock of 40MHz.
Table 56.
1. SLA6 to SLA0: Own slave address.
SxDAT7
SLA6
2
Bit
C interrupt flag (INTR) can occur in below case. (except DDC2B mode at SWENB=0)
7
6
5
4
3
2
1
0
7
7
/ACK_REP
TX_MODE
Description of the SxSTA bits
Data shift register (SxDAT: S1DAT, S2DAT)
Address register (SxADR)
INTR
Symbol
SxDAT6
BBUSY
BLOST
STOP
SLA5
SLV
GC
2
6
C unit to specify the start/stop detection time to work with the large range of
6
(1,2)
General Call Flag
Stop Flag. This bit is set when a STOP condition is received
Interrupt Flag. This bit is set when an I²C Interrupt condition is requested
Transmission mode Flag.
This bit is set when the I²C is a transmitter; otherwise this bit is reset
Bus Busy Flag.
This bit is set when the bus is being used by another master; otherwise,
this bit is reset
Bus Lost Flag.
This bit is set when the master loses the bus contention; otherwise this bit
is reset
Acknowledge Response Flag.
This bit is set when the receiver transmits the not acknowledge signal
This bit is reset when the receiver transmits the acknowledge signal
Slave mode Flag.
This bit is set when the I²C plays role in the Slave mode; otherwise this bit
is reset
SxDAT5
SLA4
5
5
SxDAT4
SLA3
4
4
SxDAT3
SLA2
3
3
Function
SxDAT2
SLA1
2
2
(Table 57
SxDAT1
SLA0
and
1
1
Table
I
2
C interface
SxDAT0
58) are
—
0
0
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