UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 96

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

USB hardware
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Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
SUSPNDI
SUSPND
6 to 0
Bit
Bit
Bit
7
7
7
6
5
4
3
2
1
0
7
7
6
5
UADD6 to
SUSPNDI
Description of the UADR Bits
USB interrupt enable register (UIEN: 0E9h)
Description of the UIEN bits
USB interrupt status register (UISTA: 0E8h)
Description of the UISTA bits
SUSPND
RESUMI
Symbol
Symbol
RXD0IE
Symbol
RSTFIE
TXD0IE
TXD1IE
USBEN
UADD0
EOPIE
RSTE
RSTE
RSTF
—
—
6
6
RSTFIE
RSTF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R
5
5
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
USB Function Enable Bit.
When USBEN is clear, the USB module will not respond to
any tokens from host.
RESET clears this bit.
Specify the USB address of the device.
RESET clears these bits.
Enable SUSPND Interrupt
Enable USB Reset; also resets the CPU and PSD modules
when bit is set to '1.'
Enable RSTF (USB Bus Reset Flag) Interrupt
Enable TXD0 Interrupt
Enable RXD0 Interrupt
Enable TXD1 Interrupt
Enable EOP Interrupt
Enable USB Resume Interrupt when it is the Suspend mode
USB Suspend Mode Flag.
To save power, this bit should be set if a 3ms constant idle
state is detected on USB bus. Setting this bit stops the clock to
the USB and causes the USB module to enter Suspend mode.
Software must clear this bit after the Resume flag (RESUMF)
is set while this Resume Interrupt Flag is serviced
Reserved
USB Reset Flag.
This bit is set when a valid RESET signal state is detected on
the D+ and D- lines. When the RSTE bit in the UIEN Register
is set, this reset detection will also generate an internal reset
signal to reset the CPU and other peripherals including the
USB module.
TXD0IE
TXD0F
4
4
RXD0IE
RXD0F
3
3
Function
Function
Function
TXD1IE
TXD1F
2
2
EOPIE
EOPF
1
1
RESUMF
RESUMI
0
0