UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 77

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
13
13.1
Analog-to-digital convertor (ADC)
The analog to digital (A/D) converter allows conversion of an analog input to a
corresponding 8-bit digital value. The A/D module has four analog inputs, which are
multiplexed into one sample and hold. The output of the sample and hold is the input into the
converter, which generates the result via successive approximation. The analog supply
voltage is connected to AV
The A/D module has two registers which are the control register ACON and A/D result
register ADAT. The register ACON, shown in
converter module. To use analog inputs, I/O is selected by P1SFS register. Also an 8-bit
prescaler ASCL divides the main system clock input down to approximately 6MHz clock that
is required for the ADC logic. Appropriate values need to be loaded into the prescaler based
upon the main MCU clock frequency prior to use.
The processing of conversion starts when the Start bit ADST is set to '1.' After one cycle, it
is cleared by hardware. The register ADAT contains the results of the A/D conversion. When
conversion is completed, the result is loaded into the ADAT the A/D Conversion Status bit
ADSF is set to '1.'
The block diagram of the A/D module is shown in Figure
ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion
is in process.
The ASCL should be loaded with a value that results in a clock rate of approximately 6MHz
for the ADC using the following formula:
Where f
The conversion time for the ADC can be calculated as follows:
ADC interrupt
The ADSF Bit in the ACON register is set to '1' when the A/D conversion is complete. The
status bit can be driven by the MCU, or it can be configured to generate a falling edge
interrupt when the conversion is complete.
The ADSF Interrupt is enabled by setting the ADSFINT Bit in the PCON register. Once the
bit is set, the external INT1 Interrupt is disabled and the ADSF Interrupt takes over as INT1.
INT1 must be configured as if it is an edge interrupt input. The INP1 pin (p3.3) is available
for general I/O functions, or Timer1 gate control.
ADC clock input = (f
ADC Conversion Time = 8 clock * 8bits * (ADC Clock) ~= 10.67usec (at 6MHz)
OSC
is the MCU clock input frequency.
OSC
REF
/ 2) / (Prescaler register value +1)
of ladder resistance of A/D module.
Table
47, controls the operation of the A/D
Analog-to-digital convertor (ADC)
Figure
34. The A/D Status bit
77/189