UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 173

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Figure 76. Input to output disable / enable
Table 127. CPLD combinatorial timing (5 V devices)
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t
Table 128. CPLD combinatorial timing (3 V devices)
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. t
Symbol
Symbol
t
t
t
t
ARPW
ARPW
t
t
t
t
PD
PD
t
t
ARP
ARD
ALE to CPLD combinatorial output (80-pin package only)
t
t
ARP
ARD
ALE to CPLD combinatorial output (80-pin package only)
PD
PD
EA
ER
EA
ER
(2)
(2)
for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and
for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and
CPLD input pin/feedback to
CPLD combinatorial output
CPLD input to CPLD output
enable
CPLD input to CPLD output
disable
CPLD register clear or
preset delay
CPLD register clear or
preset pulse width
CPLD array delay
CPLD input pin/feedback to
CPLD combinatorial output
CPLD input to CPLD output
enable
CPLD input to CPLD output
disable
CPLD register clear or
preset delay
CPLD register clear or
preset pulse width
CPLD array delay
Parameter
Parameter
ENABLE/DISABLE
INPUT TO
OUTPUT
INPUT
Conditions
Conditions
macrocell
macrocell
Any
Any
tER
Min.
Min.
10
25
Max.
Max.
tEA
20
21
21
21
11
40
43
43
40
25
aloc
aloc
+ 2
+ 2
PT
DC and AC parameters
+ 4
+ 4
PT
AI02863
Turbo
Turbo
+ 10
+ 10
+ 10
+ 10
+ 10
+ 20
+ 20
+ 20
+ 20
+ 20
off
off
rate
rate
Slew
Slew
– 2
– 2
– 2
– 2
– 6
– 6
– 6
– 6
(1)
(1)
173/189
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns