UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 136

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

I/O ports (PSD module)
24.3
24.4
24.5
24.6
24.7
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MCU I/O mode
In the MCU I/O mode, the MCU uses the I/O Ports block to expand its own I/O ports. By
setting up the CSIOP space, the ports on the PSD module are mapped into the MCU
address space. The addresses of the ports are listed in
A port pin can be put into MCU I/O mode by writing a '0' to the corresponding bit in the
Control Register. The MCU I/O direction may be changed by writing to the corresponding bit
in the Direction Register, or by the output enable product term. See
I/O
drives the pin. When configured as an input, the MCU can read the port input through the
Data In buffer. See
Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They can
be used for PLD I/O if equations are written for them in PSDabel.
PLD I/O mode
The PLD I/O mode uses a port as an input to the CPLD’s Input Macrocells (IMC), and/or as
an output from the CPLD’s Output Macrocells (OMC). The output can be tri-stated with a
control signal. This output enable control signal can be defined by a product term from the
PLD, or by resetting the corresponding bit in the Direction Register to '0.' The corresponding
bit in the Direction Register must not be set to '1' if the pin is defined for a PLD input signal in
PSDsoft. The PLD I/O mode is specified in PSDsoft by declaring the port pins, and then
writing an equation assigning the PLD I/O to a port.
Address Out mode
Address Out mode can be used to drive latched MCU addresses on to the port pins. These
port pins can, in turn, drive external devices. Either the output enable or the corresponding
bits of both the Direction Register and Control Register must be set to a '1' for pins to use
Address Out mode. This must be done by the MCU at run-time. See
address output pin assignments on Ports A and B for various MCUs.
Peripheral I/O mode
Peripheral I/O mode can be used to interface with external peripherals. In this mode, all of
Port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is
enabled by setting Bit 7 of the VM Register to a '1.'
directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for
PSEL0 and/or PSEL1 must be written in PSDsoft. The buffer is tri-stated when PSEL0 or
PSEL1 is low (not active). The PSEN signal should be “ANDed” in the PSEL equations to
disable the buffer when PSEL resides in the data space.
JTAG in-system programming (ISP)
Port C is JTAG compliant, and can be used for In-System Programming (ISP). For more
information on the JTAG Port, see
interface.
mode. When the pin is configured as an output, the content of the Data Out Register
Figure
61.
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Section 27: Programming in-circuit using the JTAG serial
Figure 62
Table
shows how Port A acts as a bi-
84.
Section 24.6: Peripheral
Table 95
for the