UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 71

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
12.2.6
As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the
data byte is at the output position of the shift register, then the '1' that was initially loaded
into the 9th position is just to the left of the MSB, and all positions to the left of that contain
zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND
and set TI. This occurs at the 10th divide-by-16 rollover after “WRITE to SBUF.”
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud rate has been established. When a transition is
detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input
shift register. Resetting the divide-by-16 counter aligns its roll-overs with the boundaries of
the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter
states of each bit time, the bit detector samples the value of RxD. The value accepted is the
value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the
value accepted during the first bit time is not '0,' the receive circuits are reset and the unit
goes back to looking for an-other 1-to-0 transition. This is to provide rejection of false start
bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the
reset of the rest of the frame will proceed.
As data bits come in from the right, '1s' shift out to the left. When the start bit arrives at the
left-most position in the shift register (which in Mode 1 is a 9-bit register), it flags the RX
Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF
and RB8, and to set RI, will be generated if, and only if, the following conditions are met at
the time the final shift pulse is generated:
1.
2.
If either of these two conditions is not met, the received frame is irretrievably lost. If both
conditions are met, the Stop bit goes into RB8, the 8 data bits go into SBUF, and RI is
activated. At this time, whether the above conditions are met or not, the unit goes back to
looking for a 1-to-0 transition in RxD.
More about Modes 2 and 3
Eleven bits are transmitted (through TxD), or received (through RxD): a Start bit (0), 8 data
bits (LSB first), a programmable 9th data bit, and a Stop bit (1). On transmit, the 9th data bit
(TB8) can be assigned the value of '0' or '1.' On receive, the data bit goes into RB8 in
SCON. The baud rate is programmable to either 1/16 or 1/32 the CPU clock frequency in
Mode 2. Mode 3 may have a variable baud rate generated from Timer 1.
Figure 30
receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1
only in the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“WRITE to SBUF” signal also loads TB8 into the 9th bit position of the transmit shift register
and flags the TX Control unit that a transmission is requested. Transmission commences at
S1P1 of the machine cycle following the next roll-over in the divide-by-16 counter. (Thus, the
bit times are synchronized to the divide-by-16 counter, not to the “WRITE to SBUF” signal.)
The transmission begins with activation of SEND, which puts the start bit at TxD. One bit
time later, DATA is activated, which enables the output bit of the transmit shift register to
TxD. The first shift pulse occurs one bit time after that. The first shift clocks a '1' (the Stop
bit) into the 9th bit position of the shift register. There-after, only zeros are clocked in. Thus,
R1 = 0, and
Either SM2 = 0, or the received Stop bit = 1.
and
Figure 32
show a functional diagram of the serial port in Modes 2 and 3. The
Standard serial interface (UART)
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