UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 19
UPSD3234A-40U6T
Manufacturer Part Number
UPSD3234A-40U6T
Description
IC MCU 8032 64KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3234A-40U6T.pdf
(189 pages)
Specifications of UPSD3234A-40U6T
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, UART/USART, USB
Peripherals
LVR, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
288KB (288K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
2.3
2.4
2.5
Program memory
The program memory consists of two Flash memories: the main Flash memory (1 or 2 Mbit)
and the Secondary Flash memory (256 Kbit). The Flash memory can be mapped to any
address space as defined by the user in the PSDsoft Tool. It can also be mapped to Data
memory space during Flash memory update or programming.
After reset, the CPU begins execution from location 0000h. As shown in
interrupt is assigned a fixed location in Program Memory. The interrupt causes the CPU to
jump to that location, where it commences execution of the service routine. External
Interrupt 0, for example, is assigned to location 0003h. If External Interrupt 0 is going to be
used, its service routine must begin at location 0003h. If the interrupt is not going to be
used, its service location is available as general purpose Program Memory.
The interrupt service locations are spaced at 8-byte intervals: 0003h for External Interrupt 0,
000Bh for Timer 0, 0013h for External Interrupt 1, 001Bh for Timer 1 and so forth. If an
interrupt service routine is short enough (as is often the case in control applications), it can
reside entirely within that 8-byte interval. Longer service routines can use a jump instruction
to skip over subsequent interrupt locations, if other interrupts are in use.
Data memory
The internal data memory is divided into four physically separated blocks: 256 bytes of
internal RAM, 128 bytes of Special Function Registers (SFRs) areas, 256 bytes of external
RAM (XRAM-DDC) and 8 Kbytes (XRAM-PSD) in the PSD module.
RAM
Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM
area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32
through 47, contain 128 directly addressable bit locations. The stack depth is only limited by
the available internal RAM space of 256 bytes.
Figure 9.
Interrupt location of program memory
Location
Interrupt
Reset
•
•
•
•
•
008Bh
0013h
000Bh
0003h
0000h
•
•
•
•
8 Bytes
AI06640
Architecture overview
Figure
9, each
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