UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 141

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
24.10
24.11
Ports A and B – functionality and structure
Ports A and B have similar functionality and structure, as shown in
can be configured to perform one or more of the following functions:
●
●
●
●
●
●
Figure 63. Port A and Port B structure
Port C – functionality and structure
Port C can be configured to perform one or more of the following functions (see
●
●
●
●
●
Port C does not support Address Out mode, and therefore no Control Register is required.
MCU I/O mode
CPLD Output – Macrocells McellAB7-McellAB0 can be connected to Port A or Port B.
McellBC7-McellBC0 can be connected to Port B or Port C.
CPLD Input – Via the Input Macrocells (IMC).
Latched Address output – Provide latched address output as per
Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew
rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain mode.
Peripheral mode – Port A only (80-pin package)
MCU I/O mode
CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C.
CPLD Input – via the Input Macrocells (IMC)
In-System Programming (ISP) – JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins
for device programming. (See
interface, for more information on JTAG programming.)
Open Drain – Port C pins can be configured in Open Drain mode
ALE
ADDRESS
MACROCELL OUTPUTS
WR
WR
WR
ENABLE PRODUCT TERM ( .OE )
CONTROL REG.
CPLD- INPUT
DATA OUT
READ MUX
DIR REG.
G
D
D
D
D
REG.
P
D
B
Q
Q
Q
Q
Section 27: Programming in-circuit using the JTAG serial
ADDRESS
A [ 7:0 ]
DATA OUT
DATA IN
OUTPUT
OUTPUT
SELECT
MUX
ENABLE OUT
MACROCELL
Figure
INPUT
I/O ports (PSD module)
Table
63. The two ports
95.
A OR B PIN
Figure
PORT
AI06605
141/189
64):