UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 33

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
2.16
Machine cycles
A machine cycle consists of a sequence of six states, numbered S1 through S6. Each state
time lasts for two oscillator periods. Thus, a machine cycle takes 12 oscillator periods or 1µs
if the oscillator frequency is 12MHz. Refer to
devices.
Each state is divided into a Phase 1 half and a Phase 2 half. State Sequence in UPSD323xx
devices shows that retrieve/execute sequences in states and phases for various kinds of
instructions.
Normally two program retrievals are generated during each machine cycle, even if the
instruction being executed does not require it. If the instruction being executed does not
need more code bytes, the CPU simply ignores the extra retrieval, and the Program Counter
is not incremented.
Execution of a one-cycle instruction
begins during State 1 of the machine cycle, when the opcode is latched into the Instruction
Register. A second retrieve occurs during S4 of the same machine cycle. Execution is
complete at the end of State 6 of this machine cycle.
The MOVX instructions take two machine cycles to execute. No program retrieval is
generated during the second cycle of a MOVX instruction. This is the only time program
retrievals are skipped. The retrieve/execute sequence for MOVX instruction is shown in
Figure 13
Table 14.
JZ rel
JNZ rel
DJNZ <byte>,rel
CJNE A,<byte>,rel
CJNE <byte>,#data,rel
Mnemonic
(d).
Conditional jump instructions
Jump if A = 0
Jump if A ≠ 0
Decrement and jump if not zero
Jump if A ≠ <byte>
Jump if <byte> ≠ #data
(Figure 13: State sequence in UPSD323xx
Operation
Table 13: State sequence in UPSD323xx
Dir.
X
X
Addressing modes
Architecture overview
Accumulator only
Accumulator only
Ind.
X
Reg.
X
X
devices)
Imm.
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X