UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 134

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

I/O ports (PSD module)
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I/O ports (PSD module)
There are four programmable I/O ports: Ports A, B, C, and D in the PSD module. Each of the
ports is eight bits except Port D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per port. The ports are configured using
PSDsoft Express Configuration or by the MCU writing to on-chip registers in the CSIOP
space. Port A is not available in the 52-pin package.
The topics discussed in this section are:
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General port architecture
The general architecture of the I/O Port block is shown in
architectures are shown in
pin has been defined, that pin is no longer available for other purposes. Exceptions are
noted.
As shown in
driven by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft
Express Configuration. Inputs to the multiplexer include the following:
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The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and
can be read by the MCU. The Data Out and macrocell outputs, Direction and Control
Registers, and port pin input are all connected to the Port Data Buffer (PDB).
General Port architecture
Port operating modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port functionality.
Output data from the Data Out register
Latched address outputs
CPLD macrocell output
External Chip Select (ECS1-ECS2) from the CPLD.
Figure
61, the ports contain an output multiplexer whose select signals are
Figure 63
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
to
Figure
66. In general, once the purpose for a port
Figure
61. Individual Port