UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 112

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Memory blocks
22
22.1
22.2
22.2.1
22.2.2
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Memory blocks
The PSD module has the following memory blocks:
●
●
●
The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are
user-defined in PSDsoft Express.
Primary Flash memory and secondary Flash memory
description
The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash
memory is divided into four equal sectors. Each sector of either memory block can be
separately protected from Program and Erase cycles.
Flash memory may be erased on a sector-by-sector basis. Flash sector erasure may be
suspended while data is read from other sectors of the block and then resumed after
reading.
During a Program or Erase cycle in Flash memory, the status can be output on Ready/Busy
(PC3). This pin is set up using PSDsoft Express Configuration.
Memory block select signals
The DPLD generates the Select signals for all the internal memory blocks (see
PLDs). Each of the eight sectors of the primary Flash memory has a Select signal (FS0-
FS7) which can contain up to three product terms. Each of the four sectors of the secondary
Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three
product terms. Having three product terms for each Select signal allows a given sector to be
mapped in Program or Data space.
Ready/Busy (PC3)
This signal can be used to output the Ready/Busy status of the Flash memory. The output
on Ready/Busy (PC3) is a '0' (Busy) when Flash memory is being written to, or when Flash
memory is being erased. The output is a '1' (Ready) when no WRITE or Erase cycle is in
progress.
Memory operation
The primary Flash memory and secondary Flash memory are addressed through the MCU
Bus. The MCU can access these memories in one of two ways:
●
●
Primary Flash memory
Secondary Flash memory
SRAM
The MCU can execute a typical bus WRITE or READ operation.
The MCU can execute a specific Flash memory instruction that consists of several
WRITE and READ operations. This involves writing specific data patterns to special
addresses within the Flash memory to invoke an embedded algorithm. These
instructions are summarized in
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Table
85.
Section 23: