UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 146

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Power management
Note:
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Figure 67. APD unit
The PSD module has a Turbo Bit in PMMR0. This bit can be set to turn the Turbo mode off
(the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve
standby current when no PLD inputs are changing (zero DC current). Even when inputs do
change, significant power can be saved at lower frequencies (AC current), compared to
when Turbo mode is on. When the Turbo mode is on, there is a significant DC current
component and the AC component is higher.
Automatic Power-down (APD) Unit and Power-down mode
The APD Unit, shown in
monitoring the activity of Address Strobe (ALE). If the APD Unit is enabled, as soon as
activity on Address Strobe (ALE) stops, a four-bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down
(PDN) goes High, and the PSD module enters Power-down mode, as discussed next.
Power-down mode
By default, if you enable the APD Unit, Power-down mode is automatically enabled. The
device enters Power-down mode if Address Strobe (ALE) remains inactive for fifteen periods
of CLKIN (PD1).
The following should be kept in mind when the PSD module is in Power-down mode:
●
●
●
Blocking CLKIN (PD1) from the PLDs does not block CLKIN (PD1) from the APD Unit.
●
●
If Address Strobe (ALE) starts pulsing again, the PSD module returns to normal
Operating mode. The PSD module also returns to normal Operating mode if either PSD
Chip Select Input (CSI, PD2) is Low or the RESET input is High.
The MCU address/data bus is blocked from all memory and PLDs.
Various signals can be blocked (prior to Power-down mode) from entering the PLDs by
setting the appropriate bits in the PMMR registers. The blocked signals include MCU
control signals and the common CLKIN (PD1).
All memories enter Standby mode and are drawing standby current. However, the PLD
and I/O ports blocks do not go into Standby mode because you don’t want to have to
wait for the logic and I/O to “wake-up” before their outputs can change. See
for Power-down mode effects on PSD module ports.
Typical standby current is of the order of microamperes. These standby current values
assume that there are no transitions on any PLD input.
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
DISABLE
FLASH/SRAM
TRANSITION
DETECTION
DETECT
EDGE
Figure
67, puts the PSD module into Power-down mode by
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
CLR
COUNTER
APD
PD
PD
DISABLE BUS
INTERFACE
PLD
CSIOP SELECT
FLASH SELECT
SRAM SELECT
POWER DOWN
( PDN )
SELECT
Table 102
AI06608