UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 130

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PLDs
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The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD
module internal data bus and can be directly accessed by the MCU. This enables the MCU
software to load data into the Output Macrocells (OMC) or read data from both the Input and
Output Macrocells (IMC and OMC).
This feature allows efficient implementation of system logic and eliminates the need to
connect the data bus to the AND Array as required in most standard PLD macrocell
architectures.
Figure 58. Macrocell and I/O ports
Output macrocell (OMC)
Eight of the Output Macrocells (OMC) are connected to Ports A and B pins and are named
as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and
are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in
PSDsoft, the Macrocell Allocator block assigns it to either Port A or B. The same is true for a
McellBC output on Port B or C.
The Output Macrocell (OMC) architecture is shown in
there are native product terms available from the AND Array, and borrowed product terms
available (if unused) from other Output Macrocells (OMC). The polarity of the product term
is controlled by the XOR gate. The Output Macrocell (OMC) can implement either sequential
logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the
sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and
has a feedback path to the AND Array inputs.
The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR
type in PSDsoft. The flip-flop’s clock, preset, and clear inputs may be driven from a product
term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip-
PRODUCT TERMS
MACROCELLS
FROM OTHER
PRODUCT TERM
PT
CLOCK
PT CLEAR
GLOBAL
CLOCK
CLOCK
SELECT
ALLOCATOR
PRODUCT TERMS
PT INPUT LATCH GATE/CLOCK
CPLD MACROCELLS
UP TO 10
POLARITY
SELECT
MACROCELL FEEDBACK
PT OUTPUT ENABLE ( OE )
I/O PORT INPUT
PT PRESET
Table 92
PR DI LD
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
D/T
CK
D/T/JK FF
SELECT
MCU DATA IN
CL
Q
MCU LOAD
MCU ADDRESS / DATA BUS
SELECT
COMB.
/REG
shows the macrocells and port assignment.
MACROCELL
CONTROL
OUT TO
DATA
LOAD
MACROCELL
MCU
I/O PORT
ALLOC.
TO
OUTPUT
CPLD
Figure
59. As shown in the figure,
DATA
CPLD OUTPUT
ALE
ADDRESS OUT
I/O PORTS
WR
WR
INPUT MACROCELLS
LATCHED
PDR
D
TO OTHER I/O PORTS
D
REG.
DIR
INPUT
Q
Q
MUX
SELECT
Q
Q D
D
G
AI06602
I/O PIN