UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 114

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Memory blocks
Table 85.
114/189
Program a Flash
Byte
Flash Sector
Erase
Flash Bulk
Erase
Suspend Sector
Erase
Resume Sector
Erase
RESET
Unlock Bypass
Unlock Bypass
Program
Unlock Bypass
Reset
Instruction
(13)
(7,13)
(13)
(11)
(12)
(10)
(6)
(9)
Instructions (continued)
1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label
2. All values are in hexadecimal.
3. X = Don’t care. Addresses of the form XXXXh, in this table, must be even addresses
4. RA = Address of the memory location to be read
5. RD = Data READ from location RA during the READ cycle
6. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of
7. PA is an even address for PSD in Word Programming mode.
8. PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe
9. SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3)
10. Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) signals are active High, and are defined in PSDsoft
11. Only address Bits A11-A0 are used in instruction decoding.
12. No Unlock or instruction cycles are required when the device is in the READ mode
13. The RESET instruction is required to return to the READ mode after reading the Sector Protection Status,
14. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.
15. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector
16. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
17. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is
18. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the
19. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
WRITE Strobe (WR, CNTL0).
(WR, CNTL0)
of the sector to be erased, or verified, must be Active (High).
Express.
or if the Error flag bit (DQ5/DQ13) goes High.
Select is active, and (A1,A0)=(1,0)
in the Unlock Bypass mode.
Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction
is valid only during a Sector Erase cycle.
FS0-FS7 or
CSBOOT0-
CSBOOT3
1
1
1
1
1
1
1
1
1
AAh@
X555h
AAh@
X555h
AAh@
X555h
B0h@
XXXXh
30h@
XXXXh
F0h@
XXXXh
AAh@
X555h
A0h@
XXXXh
90h@
XXXXh
Cycle 1
55h@
XAAAh
55h@
XAAAh
55h@
XAAAh
55h@
XAAAh
PD@ PA
00h@
XXXXh
Cycle 2
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
A0h@
X555h
80h@
X555h
80h@
X555h
20h@
X555h
Cycle 3
PD@ PA
AAh@
X555h
AAh@
X555h
Cycle 4
55h@
XAAAh
55h@
XAAAh
Cycle 5
30h@ SA
10h@
X555h
Cycle 6
30h
next SA
Cycle 7
7
@