UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 97

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Table 68.
Table 69.
TSEQ0
Bit
4
3
2
1
0
7
Description of the UISTA bits (continued)
RESUMF
USB Endpoint0 transmit control register (UCON0: 0EAh)
Symbol
STALL0
RXD0F
TXD0F
TXD1F
EOPF
6
TX0E
R/W
R/W
R/W
R/W
R/W
R/W
5
Endpoint0 Data Transmit Flag.
This bit is set after the data stored in Endpoint 0 transmit
buffers has been sent and an ACK handshake packet from the
host is received. Once the next set of data is ready in the
transmit buffers, software must clear this flag. To enable the
next data packet transmission, TX0E must also be set. If
TXD0F Bit is not cleared, a NAK handshake will be returned in
the next IN transactions. RESET clears this bit.
Endpoint0 Data Receive Flag.
This bit is set after the USB module has received a data
packet and responded with ACK handshake packet. Software
must clear this flag after all of the received data has been
read. Software must also set RX0E Bit to one to enable the
next data packet reception. If RXD0F Bit is not cleared, a NAK
handshake will be returned in the next OUT transaction.
RESET clears this bit.
Endpoint1 / Endpoint2 Data Transmit Flag.
This bit is shared by Endpoints 1 and Endpoints 2. It is set
after the data stored in the shared Endpoint 1/ Endpoint 2
transmit buffer has been sent and an ACK handshake packet
from the host is received. Once the next set of data is ready in
the transmit buffers, software must clear this flag. To enable
the next data packet transmission, TX1E must also be set. If
TXD1F Bit is not cleared, a NAK handshake will be returned in
the next IN transaction. RESET clears this bit.
End of Packet Flag.
This bit is set when a valid End of Packet sequence is
detected on the D+ and D-line. Software must clear this flag.
RESET clears this bit.
Resume Flag.
This bit is set when USB bus activity is detected while the
SUSPND Bit is set.
Software must clear this flag. RESET clears this bit.
RX0E
4
TP0SIZ3
3
Function
TP0SIZ2
2
TP0SIZ1
1
USB hardware
TP0SIZ0
0
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