UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 122

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Memory blocks
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Table 87.
1. Bit Definitions:
Table 88.
1. Bit Definitions:
Reset Flash
The Reset Flash instruction consists of one WRITE cycle (see
optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:
●
●
The Reset Flash instruction puts the Flash memory back into normal READ mode. If an
Error condition has occurred (and the device has set the Error Flag bit (DQ5) to '1' the Flash
memory is put back into normal READ mode within 25µs of the Reset Flash instruction
having been issued. The Reset Flash instruction is ignored when it is issued during a
Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any
on-going Sector Erase cycle, and returns the Flash memory to the normal READ mode
within 25µs.
Reset (RESET) signal
A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash
memory to the READ mode. When the reset occurs during a Program or Erase cycle, the
Flash memory takes up to 25μs to return to the READ mode. It is recommended that the
Reset (RESET) pulse (except for Power-on RESET, as described in
timing and device status at
for the MCU to retreive the bootstrap instructions after the reset cycle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select
(RS0) can contain up to two product terms, allowing flexible memory mapping.
Security_B
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Sec<i>_Prot
Sec<i>_Prot
Sec<i>_Prot
Sec<i>_Prot
Security_Bit
Bit 7
Bit 7
Reading the Flash Protection Status or Flash ID
An Error condition has occurred (and the device has set the Error Flag bit (DQ5) to '1'
during a Flash memory Program or Erase cycle.
it
Sector protection/security bit definition – Flash protection register
Sector protection/security bit definition – secondary Flash protection
register
Not used
Bit 6
Bit 6
1 = Primary Flash memory or secondary Flash memory Sector <i> is write-protected.
0 = Primary Flash memory or secondary Flash memory Sector <i> is not write-protected.
1 = Secondary Flash memory Sector <i> is write-protected.
0 = Secondary Flash memory Sector <i> is not write-protected.
0 = Security Bit in device has not been set; 1 = Security Bit in device has been set.
Not used
Bit 5
Bit 5
reset) be at least 25µs so that the Flash memory is always ready
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Not used
Bit 4
Bit 4
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit 3
Bit 3
Bit 2
Bit 2
Table
Section 26: RESET
85). It can also be
Bit 1
Bit 1
Bit 0
Bit 0