UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 55

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
9
9.1
9.2
Note:
Supervisory
There are four ways to invoke a reset and initialize the UPSD323xx devices.
1.
2.
3.
4.
The RESET mechanism is illustrated in
Each RESET source will cause an internal reset signal active. The CPU responds by
executing an internal reset and puts the internal registers in a defined state. This internal
reset is also routed as an active low reset input to the PSD module.
Figure 19. RESET configuration
External reset
The RESET pin is connected to a Schmitt trigger for noise reduction. A RESET is
accomplished by holding the RESET pin LOW for at least 1ms at power up while the
oscillator is running. Refer to AC spec on other RESET timing requirements.
Low V
An internal reset is generated by the LVR circuit when the V
threshold. After V
asserted for 10ms before it is released. On initial power-up the LVR is enabled (default).
After power-up the LVR can be disabled via the LVREN Bit in the PCON Register.
The LVR logic is still functional in both the Idle and Power-down modes.
The reset threshold:
●
●
This logic supports approximately 0.1 V of hysteresis and 1 µs noise-cancelling delay.
5 V operation:
3.3 V operation: 2.5 V ± 0.2 V
Via the external RESET pin
Via the internal LVR block
Via USB bus reset signaling
Via Watchdog Timer (WDT)
DD
Reset
USB Reset
voltage reset
WDT
LVR
RSTE
DD
reaching back up to the reset threshold, the RESET signal will remain
4 V ± 0.25 V
Timer
10ms
Figure
Cancel
Noise
10ms at 40Mhz
50ms at 8Mhz
S
R
19.
Q
DD
Clock
CPU
Sync
drops below the reset
“ Active Low
PERI.
CPU
&
PSD_RST
AI06621
Supervisory
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