UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 127

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
23
23.1
PLDs
PLDs bring programmable logic functionality to the UPSD. After specifying the logic for the
PLDs using PSDsoft Express, the logic is programmed into the device and available upon
Power-up.
Table 90.
Note: 1. These inputs are not available in the 52-pin package.
The PSD module contains two PLDs: the Decode PLD (DPLD), and the Complex PLD
(CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in
Section 23.2: Decode PLD
shows the configuration of the PLDs.
The DPLD performs address decoding for Select signals for PSD module components, such
as memory, registers, and I/O ports.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be constructed
using the Output Macrocells (OMC), Input Macrocells (IMC), and the AND Array. The CPLD
can also be used to generate External Chip Select (ECS1-ECS2) signals.
The AND Array is used to form product terms. These product terms are specified using
PSDsoft. The PLD input signals consist of internal MCU signals and external inputs from the
I/O ports. The input signals are shown in
Turbo bit in PSD module
The PLDs can minimize power consumption by switching off when inputs remain unchanged
for an extended time of about 70ns. Resetting the Turbo bit to '0' (Bit 3 of PMMR0)
automatically places the PLDs into standby if no inputs are changing. Turning the Turbo
mode off increases propagation delays while reducing power consumption.
MCU Address Bus
MCU Control Signals
RESET
Power-down
Port A Input Macrocells
Port B Input Macrocells
Port C Input Macrocells
Port D Inputs
Page Register
Macrocell AB Feedback
Macrocell BC Feedback
Flash memory Program Status bit
DPLD and CPLD Inputs
Input Source
(1)
(DPLD), and
A15-A0
PSEN, RD, WR, ALE
RST
PDN
PA7-PA0
PB7-PB0
PC2-4, PC7
PD2-PD1
PGR7-PGR0
MCELLAB.FB7-FB0
MCELLBC.FB7-FB0
Ready/Busy
Section 23.3: Complex PLD
Table
90.
Input Name
(CPLD).
Number of
Figure 57
Signals
16
4
1
1
8
8
4
2
8
8
8
1
127/189
PLDs