UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 113

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
22.3
Table 85.
READ
READ Sector
Protection
Instruction
(5)
(6,8,13)
Typically, the MCU can read Flash memory using READ operations, just as it would read a
ROM device. However, Flash memory can only be altered using specific Erase and Program
instructions. For example, the MCU cannot write a single byte directly to Flash memory as it
would write a byte to RAM. To program a byte into Flash memory, the MCU must execute a
Program instruction, then test the status of the Program cycle. This status test is achieved
by a READ operation or polling Ready/Busy (PC3).
Instructions
An instruction consists of a sequence of specific operations. Each received byte is
sequentially decoded by the PSD module and not executed as a standard WRITE operation.
The instruction is executed when the correct number of bytes are properly received and the
time between two consecutive bytes is shorter than the time-out period. Some instructions
are structured to include READ operations after the initial WRITE operations.
The instruction must be followed exactly. Any invalid combination of instruction bytes or
time-out between two consecutive bytes while addressing Flash memory resets the device
logic into READ mode (Flash memory is read like a ROM device).
The Flash memory supports the instructions summarized in
●
●
●
●
●
●
These instructions are detailed in
two bytes of an instruction are the coded cycles and are followed by an instruction byte or
confirmation byte. The coded cycles consist of writing the data AAh to address X555h
during the first cycle and data 55h to address XAAAh during the second cycle. Address
signals A15-A12 are Don’t Care during the instruction WRITE cycles. However, the
appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected.
The primary and secondary Flash memories have the same instruction set (except for Read
Primary Flash Identifier). The Sector Select signals determine which Flash memory is to
receive and execute the instruction. The primary Flash memory is selected if any one of
Sector Select (FS0-FS7) is High, and the secondary Flash memory is selected if any one of
Sector Select (CSBOOT0-CSBOOT3) is High.
Instructions
FS0-FS7 or
CSBOOT0-
Erase memory by chip or sector
Suspend or resume sector erase
Program a Byte
RESET to READ mode
Read Sector Protection Status
Bypass
CSBOOT3
1
1
“Read”
RD @ RA
AAh@
X555h
Cycle 1
55h@
XAAAh
Cycle 2
Table
90h@
X555h
85. For efficient decoding of the instructions, the first
Cycle 3
Read
status @
XX02h
Cycle 4
Table
Cycle 5
85:
Cycle 6
Memory blocks
Cycle 7
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