UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 91

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Table 62.
SWENB
0
1
In this state, the DDC unit is disabled. The DDC
SRAM cannot be accessed by the MCU. No MCU
interrupt and no DDC activity will occur.
MCU cannot access internal DDC SRAM: DDC
SRAM address space is re-assigned to external
data space.
In this state, the DDC unit is disabled, BUT with
SWENB=1, the MCU can access the SRAM. This
state is used to load the DDC SRAM with the
correct data for automatic modes. No MCU
interrupt and no DDC activity will occur.
MCU can access DDC SRAM: data space FF00h-
FFFFh is dedicated to DDC SRAM.
Table 61.
SWNEB bit function
DDCCON.bit2 = 0 (DDC1 mode Disable) or
Bit
S1CON.bit6 = 0 (I
3
2
1
0
DDC1 or DDC2b mode Disabled
DDC1_Int
Description of the DDCON register bits (continued)
DDC1EN
SWHINT
Symbol
Mode
2
C mode Disable)
For DDC1 mode Operation Only:
0 = No DDC1 Interrupt
1 = DDC1 Interrupt request. Set by HW and should be cleared by SW
interrupt service routine.
Note1: This bit is set in the 9th V
0 = DDC1 mode is disabled – V
The DDC unit will still respond to DDC2b requests. –provided I2C
enabled.(Default)
1 = DDC1 mode is enabled.
Set by hardware when the DDC unit switches from DDC1 to DDC2b
modes.
0 = No interrupt request.
1 = Switch to DDC2b mode (Interrupt pending)
Set by HW and should be cleared by SW interrupt service routine.
Note1: This bit has no connection with SWENB.
Current Mode Indication Bit:
0 = Unit is in DDC1 mode
1 = Unit is in DDC2b mode
Note: When the DDC unit transitions to DDC2b mode, the DDC unit will
stay in DDC2b mode until the DDC unit is disabled, or the system is reset.
In this state, the DDC is enabled and the unit is in
automatic mode. The DDC SRAM cannot be
accessed by the MCU – only the DDC unit has
access.
MCU cannot access internal DDC SRAM: data
space FF00h-FFFFh is dedicated to DDC SRAM.
In this state, the DDC SRAM can be accessed by
the MCU. The DDC unit does not use the DDC
SRAM when SWENB=1. Since the DDC unit is in
manual mode, the DDC unit generates an MCU
interrupt for each byte transferred. The byte
transferred is held in the I
MCU can access DDC SRAM.
DDCCON.bit2 = 1 (DDC1 mode Enable) or
S1CON.bit6 = 1 (I
SYNC
Function
DDC1 or DDC2b mode Enabled
CLK
at DDC1 Enable mode. (SWENB=1)
is ignored.
2
2
C mode Enable)
C S1DAT SFR register.
DDC interface
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