UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 132

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PLDs
23.5.1
23.5.2
23.5.3
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Loading and Reading the Output Macrocells (OMC)
The Output Macrocells (OMC) block occupies a memory location in the MCU address
space, as defined by the CSIOP block (see
flops in each of the 16 Output Macrocells (OMC) can be loaded from the data bus by a
MCU. Loading the Output Macrocells (OMC) with data from the MCU takes priority over
internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be
overridden by the MCU. The ability to load the flip-flops and read them back is useful in such
applications as loadable counters and shift registers, mailboxes, and handshaking protocols.
Data can be loaded to the Output Macrocells (OMC) on the trailing edge of WRITE Strobe
(WR, edge loading) or during the time that WRITE Strobe (WR) is active (level loading). The
method of loading is specified in PSDsoft Express Configuration.
Figure 59. CPLD output macrocell
OMC mask register
There is one Mask Register for each of the two groups of eight Output Macrocells (OMC).
The Mask Registers can be used to block the loading of data to individual Output Macrocells
(OMC). The default value for the Mask Registers is 00h, which allows loading of the Output
Macrocells (OMC). When a given bit in a Mask Register is set to a '1,' the MCU is blocked
from writing to the associated Output Macrocells (OMC). For example, suppose McellAB0-
McellAB3 are being used for a state machine. You would not want a MCU write to McellAB
to overwrite the state machine registers. Therefore, you would want to load the Mask
Register for McellAB (Mask Macrocell AB) with the value 0Fh.
Output enable of the OMC
The Output Macrocells (OMC) block can be connected to an I/O port pin as a PLD output.
The output enable of each port pin driver is controlled by a single product term from the
ALLOCATOR
CLKIN
PT CLK
PT
PT
MACROCELL CS
PT
PT
MASK
REG.
FEEDBACK ( .FB )
POLARITY
RD
WR
SELECT
PORT INPUT
CLEAR ( .RE )
ENABLE (.OE)
PRESET(.PR)
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
MUX
Section 24: I/O ports (PSD
IN
LD
DIN
CLR
PROGRAMMABLE
FF ( D/T/JK /SR )
PR
Q
COMB/REG
SELECT
MUX
MCU DATA BUS
MACROCELL
ALLOCATOR
DIRECTION
REGISTER
D [ 7:0 ]
module)). The flip-
MACROCELL
PORT
DRIVER
INPUT
AI06617
I/O PIN